Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0-only
2 : /*
3 : * Copyright (C) 2013--2024 Intel Corporation
4 : */
5 :
6 : #include <linux/cacheflush.h>
7 : #include <linux/delay.h>
8 : #include <linux/device.h>
9 : #include <linux/io.h>
10 : #include <linux/spinlock.h>
11 : #include <linux/types.h>
12 :
13 : #include "ipu6-bus.h"
14 : #include "ipu6-cpd.h"
15 : #include "ipu6-fw-com.h"
16 : #include "ipu6-isys.h"
17 : #include "ipu6-platform-isys-csi2-reg.h"
18 : #include "ipu6-platform-regs.h"
19 :
20 : static const char send_msg_types[N_IPU6_FW_ISYS_SEND_TYPE][32] = {
21 : "STREAM_OPEN",
22 : "STREAM_START",
23 : "STREAM_START_AND_CAPTURE",
24 : "STREAM_CAPTURE",
25 : "STREAM_STOP",
26 : "STREAM_FLUSH",
27 : "STREAM_CLOSE"
28 : };
29 :
30 0 : static int handle_proxy_response(struct ipu6_isys *isys, unsigned int req_id)
31 : {
32 0 : struct device *dev = &isys->adev->auxdev.dev;
33 : struct ipu6_fw_isys_proxy_resp_info_abi *resp;
34 : int ret;
35 :
36 0 : resp = ipu6_recv_get_token(isys->fwcom, IPU4_BASE_PROXY_RECV_QUEUES);
37 0 : if (!resp)
38 : return 1;
39 :
40 0 : dev_dbg(dev, "Proxy response: id %u, error %u, details %u\n",
41 : resp->request_id, resp->error_info.error,
42 : resp->error_info.error_details);
43 :
44 0 : ret = req_id == resp->request_id ? 0 : -EIO;
45 :
46 0 : ipu6_recv_put_token(isys->fwcom, IPU4_BASE_PROXY_RECV_QUEUES);
47 :
48 0 : return ret;
49 : }
50 :
51 0 : int ipu6_fw_isys_send_proxy_token(struct ipu6_isys *isys,
52 : unsigned int req_id,
53 : unsigned int index,
54 : unsigned int offset, u32 value)
55 : {
56 0 : struct ipu6_fw_com_context *ctx = isys->fwcom;
57 0 : struct device *dev = &isys->adev->auxdev.dev;
58 : struct ipu6_fw_proxy_send_queue_token *token;
59 : unsigned int timeout = 1000;
60 : int ret;
61 :
62 0 : dev_dbg(dev,
63 : "proxy send: req_id 0x%x, index %d, offset 0x%x, value 0x%x\n",
64 : req_id, index, offset, value);
65 :
66 0 : token = ipu6_send_get_token(ctx, IPU4_BASE_PROXY_SEND_QUEUES);
67 0 : if (!token)
68 : return -EBUSY;
69 :
70 0 : token->request_id = req_id;
71 0 : token->region_index = index;
72 0 : token->offset = offset;
73 0 : token->value = value;
74 0 : ipu6_send_put_token(ctx, IPU4_BASE_PROXY_SEND_QUEUES);
75 :
76 : do {
77 : usleep_range(100, 110);
78 0 : ret = handle_proxy_response(isys, req_id);
79 0 : if (!ret)
80 : break;
81 0 : if (ret == -EIO) {
82 0 : dev_err(dev, "Proxy respond with unexpected id\n");
83 0 : break;
84 : }
85 0 : timeout--;
86 0 : } while (ret && timeout);
87 :
88 0 : if (!timeout)
89 0 : dev_err(dev, "Proxy response timed out\n");
90 :
91 : return ret;
92 : }
93 :
94 5 : int ipu6_fw_isys_complex_cmd(struct ipu6_isys *isys,
95 : const unsigned int stream_handle,
96 : void *cpu_mapped_buf,
97 : dma_addr_t dma_mapped_buf,
98 : size_t size, u16 send_type)
99 : {
100 5 : struct ipu6_fw_com_context *ctx = isys->fwcom;
101 5 : struct device *dev = &isys->adev->auxdev.dev;
102 : struct ipu6_fw_send_queue_token *token;
103 :
104 5 : if (send_type >= N_IPU6_FW_ISYS_SEND_TYPE)
105 : return -EINVAL;
106 :
107 5 : dev_dbg(dev, "send_token: %s\n", send_msg_types[send_type]);
108 :
109 : /*
110 : * Time to flush cache in case we have some payload. Not all messages
111 : * have that
112 : */
113 5 : if (cpu_mapped_buf)
114 3 : clflush_cache_range(cpu_mapped_buf, size);
115 :
116 5 : token = ipu6_send_get_token(ctx,
117 5 : stream_handle + IPU4_BASE_MSG_SEND_QUEUES);
118 5 : if (!token)
119 : return -EBUSY;
120 :
121 5 : token->payload = dma_mapped_buf;
122 5 : token->buf_handle = (unsigned long)cpu_mapped_buf;
123 5 : token->send_type = send_type;
124 :
125 5 : ipu6_send_put_token(ctx, stream_handle + IPU4_BASE_MSG_SEND_QUEUES);
126 :
127 5 : return 0;
128 : }
129 :
130 2 : int ipu6_fw_isys_simple_cmd(struct ipu6_isys *isys,
131 : const unsigned int stream_handle, u16 send_type)
132 : {
133 2 : return ipu6_fw_isys_complex_cmd(isys, stream_handle, NULL, 0, 0,
134 : send_type);
135 : }
136 :
137 : // Refactoring needed for silent_reset - upstream candidate?
138 1 : int ipu6_fw_isys_open(struct ipu6_isys *isys)
139 : {
140 1 : const struct ipu6_isys_internal_pdata *ipdata = isys->pdata->ipdata;
141 1 : struct ipu6_bus_device *adev = isys->adev;
142 : int ret = 0;
143 :
144 : if (!isys->resetting)
145 : lockdep_assert_held(&isys->mutex);
146 :
147 1 : ipu6_configure_spc(adev->isp, &ipdata->hw_variant,
148 : IPU6_CPD_PKG_DIR_ISYS_SERVER_IDX, isys->pdata->base,
149 : adev->pkg_dir, adev->pkg_dir_dma_addr);
150 :
151 : /*
152 : * Buffers could have been left to wrong queue at last closure.
153 : * Move them now back to empty buffer queue.
154 : */
155 1 : ipu6_cleanup_fw_msg_bufs(isys);
156 :
157 1 : if (isys->fwcom) {
158 : /*
159 : * Something went wrong in previous shutdown. As we are now
160 : * restarting isys we can safely delete old context.
161 : */
162 0 : dev_info(&adev->auxdev.dev, "Clearing old context\n");
163 0 : ipu6_fw_isys_cleanup(isys);
164 : }
165 :
166 1 : ret = ipu6_fw_isys_init(isys, ipdata->num_parallel_streams);
167 :
168 1 : return ret;
169 : }
170 :
171 1 : int ipu6_fw_isys_close(struct ipu6_isys *isys)
172 : {
173 1 : struct device *dev = &isys->adev->auxdev.dev;
174 : int retry = IPU6_ISYS_CLOSE_RETRY;
175 : unsigned long flags;
176 : void *fwcom;
177 : int ret;
178 :
179 : // Ambu specific: for silent_reset feature
180 : if (!isys->resetting)
181 : lockdep_assert_held(&isys->mutex);
182 :
183 : /*
184 : * Stop the isys fw. Actual close takes
185 : * some time as the FW must stop its actions including code fetch
186 : * to SP icache.
187 : * spinlock to wait the interrupt handler to be finished
188 : */
189 1 : spin_lock_irqsave(&isys->power_lock, flags);
190 1 : ret = ipu6_fw_com_close(isys->fwcom);
191 1 : fwcom = isys->fwcom;
192 1 : isys->fwcom = NULL;
193 : spin_unlock_irqrestore(&isys->power_lock, flags);
194 1 : if (ret)
195 0 : dev_err(dev, "Device close failure: %d\n", ret);
196 :
197 : /* release probably fails if the close failed. Let's try still */
198 : do {
199 : usleep_range(400, 500);
200 1 : ret = ipu6_fw_com_release(fwcom, 0);
201 1 : retry--;
202 1 : } while (ret && retry);
203 :
204 1 : if (ret) {
205 0 : dev_err(dev, "Device release time out %d\n", ret);
206 0 : spin_lock_irqsave(&isys->power_lock, flags);
207 0 : isys->fwcom = fwcom;
208 : spin_unlock_irqrestore(&isys->power_lock, flags);
209 : }
210 :
211 1 : return ret;
212 : }
213 :
214 0 : void ipu6_fw_isys_cleanup(struct ipu6_isys *isys)
215 : {
216 : int ret;
217 :
218 0 : ret = ipu6_fw_com_release(isys->fwcom, 1);
219 0 : if (ret < 0)
220 0 : dev_warn(&isys->adev->auxdev.dev,
221 : "Device busy, fw_com release failed.");
222 0 : isys->fwcom = NULL;
223 0 : }
224 :
225 1 : static void start_sp(struct ipu6_bus_device *adev)
226 : {
227 : struct ipu6_isys *isys = ipu6_bus_get_drvdata(adev);
228 1 : void __iomem *spc_regs_base = isys->pdata->base +
229 1 : isys->pdata->ipdata->hw_variant.spc_offset;
230 : u32 val = IPU6_ISYS_SPC_STATUS_START |
231 : IPU6_ISYS_SPC_STATUS_RUN |
232 : IPU6_ISYS_SPC_STATUS_CTRL_ICACHE_INVALIDATE;
233 :
234 2 : val |= isys->icache_prefetch ? IPU6_ISYS_SPC_STATUS_ICACHE_PREFETCH : 0;
235 :
236 : writel(val, spc_regs_base + IPU6_ISYS_REG_SPC_STATUS_CTRL);
237 1 : }
238 :
239 2 : static int query_sp(struct ipu6_bus_device *adev)
240 : {
241 : struct ipu6_isys *isys = ipu6_bus_get_drvdata(adev);
242 2 : void __iomem *spc_regs_base = isys->pdata->base +
243 2 : isys->pdata->ipdata->hw_variant.spc_offset;
244 : u32 val;
245 :
246 : val = readl(spc_regs_base + IPU6_ISYS_REG_SPC_STATUS_CTRL);
247 : /* return true when READY == 1, START == 0 */
248 2 : val &= IPU6_ISYS_SPC_STATUS_READY | IPU6_ISYS_SPC_STATUS_START;
249 :
250 2 : return val == IPU6_ISYS_SPC_STATUS_READY;
251 : }
252 :
253 1 : static int ipu6_isys_fwcom_cfg_init(struct ipu6_isys *isys,
254 : struct ipu6_fw_com_cfg *fwcom,
255 : unsigned int num_streams)
256 : {
257 : unsigned int max_send_queues, max_sram_blocks, max_devq_size;
258 : struct ipu6_fw_syscom_queue_config *input_queue_cfg;
259 : struct ipu6_fw_syscom_queue_config *output_queue_cfg;
260 1 : struct device *dev = &isys->adev->auxdev.dev;
261 : int type_proxy = IPU6_FW_ISYS_QUEUE_TYPE_PROXY;
262 : int type_dev = IPU6_FW_ISYS_QUEUE_TYPE_DEV;
263 : int type_msg = IPU6_FW_ISYS_QUEUE_TYPE_MSG;
264 : int base_dev_send = IPU4_BASE_DEV_SEND_QUEUES;
265 : int base_msg_send = IPU4_BASE_MSG_SEND_QUEUES;
266 : int base_msg_recv = IPU4_BASE_MSG_RECV_QUEUES;
267 : struct ipu6_fw_isys_fw_config *isys_fw_cfg;
268 : u32 num_in_message_queues;
269 : unsigned int max_streams;
270 : unsigned int size;
271 : unsigned int i;
272 :
273 1 : max_streams = isys->pdata->ipdata->max_streams;
274 1 : max_send_queues = isys->pdata->ipdata->max_send_queues;
275 1 : max_sram_blocks = isys->pdata->ipdata->max_sram_blocks;
276 1 : max_devq_size = isys->pdata->ipdata->max_devq_size;
277 1 : num_in_message_queues = clamp(num_streams, 1U, max_streams);
278 : isys_fw_cfg = devm_kzalloc(dev, sizeof(*isys_fw_cfg), GFP_KERNEL);
279 1 : if (!isys_fw_cfg)
280 : return -ENOMEM;
281 :
282 1 : isys_fw_cfg->num_send_queues[type_proxy] = IPU4_N_MAX_PROXY_SEND_QUEUES;
283 1 : isys_fw_cfg->num_send_queues[type_dev] = IPU4_N_MAX_DEV_SEND_QUEUES;
284 1 : isys_fw_cfg->num_send_queues[type_msg] = num_in_message_queues;
285 1 : isys_fw_cfg->num_recv_queues[type_proxy] = IPU4_N_MAX_PROXY_RECV_QUEUES;
286 : /* Common msg/dev return queue */
287 1 : isys_fw_cfg->num_recv_queues[type_dev] = 0;
288 1 : isys_fw_cfg->num_recv_queues[type_msg] = 1;
289 :
290 1 : size = sizeof(*input_queue_cfg) * max_send_queues;
291 1 : input_queue_cfg = devm_kzalloc(dev, size, GFP_KERNEL);
292 1 : if (!input_queue_cfg)
293 : return -ENOMEM;
294 :
295 : size = sizeof(*output_queue_cfg) * IPU4_N_MAX_RECV_QUEUES;
296 : output_queue_cfg = devm_kzalloc(dev, size, GFP_KERNEL);
297 1 : if (!output_queue_cfg)
298 : return -ENOMEM;
299 :
300 1 : fwcom->input = input_queue_cfg;
301 1 : fwcom->output = output_queue_cfg;
302 :
303 1 : fwcom->num_input_queues = isys_fw_cfg->num_send_queues[type_proxy] +
304 1 : isys_fw_cfg->num_send_queues[type_dev] +
305 1 : isys_fw_cfg->num_send_queues[type_msg];
306 :
307 1 : fwcom->num_output_queues = isys_fw_cfg->num_recv_queues[type_proxy] +
308 1 : isys_fw_cfg->num_recv_queues[type_dev] +
309 1 : isys_fw_cfg->num_recv_queues[type_msg];
310 :
311 : /* SRAM partitioning. Equal partitioning is set. */
312 9 : for (i = 0; i < max_sram_blocks; i++) {
313 8 : if (i < num_in_message_queues)
314 8 : isys_fw_cfg->buffer_partition.num_gda_pages[i] =
315 : (IPU6_DEVICE_GDA_NR_PAGES *
316 8 : IPU6_DEVICE_GDA_VIRT_FACTOR) /
317 : num_in_message_queues;
318 : else
319 0 : isys_fw_cfg->buffer_partition.num_gda_pages[i] = 0;
320 : }
321 :
322 : /* FW assumes proxy interface at fwcom queue 0 */
323 2 : for (i = 0; i < isys_fw_cfg->num_send_queues[type_proxy]; i++) {
324 1 : input_queue_cfg[i].token_size =
325 : sizeof(struct ipu6_fw_proxy_send_queue_token);
326 1 : input_queue_cfg[i].queue_size = IPU6_ISYS_SIZE_PROXY_SEND_QUEUE;
327 : }
328 :
329 2 : for (i = 0; i < isys_fw_cfg->num_send_queues[type_dev]; i++) {
330 1 : input_queue_cfg[base_dev_send + i].token_size =
331 : sizeof(struct ipu6_fw_send_queue_token);
332 1 : input_queue_cfg[base_dev_send + i].queue_size = max_devq_size;
333 : }
334 :
335 9 : for (i = 0; i < isys_fw_cfg->num_send_queues[type_msg]; i++) {
336 8 : input_queue_cfg[base_msg_send + i].token_size =
337 : sizeof(struct ipu6_fw_send_queue_token);
338 8 : input_queue_cfg[base_msg_send + i].queue_size =
339 : IPU6_ISYS_SIZE_SEND_QUEUE;
340 : }
341 :
342 2 : for (i = 0; i < isys_fw_cfg->num_recv_queues[type_proxy]; i++) {
343 1 : output_queue_cfg[i].token_size =
344 : sizeof(struct ipu6_fw_proxy_resp_queue_token);
345 1 : output_queue_cfg[i].queue_size =
346 : IPU6_ISYS_SIZE_PROXY_RECV_QUEUE;
347 : }
348 : /* There is no recv DEV queue */
349 2 : for (i = 0; i < isys_fw_cfg->num_recv_queues[type_msg]; i++) {
350 1 : output_queue_cfg[base_msg_recv + i].token_size =
351 : sizeof(struct ipu6_fw_resp_queue_token);
352 1 : output_queue_cfg[base_msg_recv + i].queue_size =
353 : IPU6_ISYS_SIZE_RECV_QUEUE;
354 : }
355 :
356 1 : fwcom->dmem_addr = isys->pdata->ipdata->hw_variant.dmem_offset;
357 1 : fwcom->specific_addr = isys_fw_cfg;
358 1 : fwcom->specific_size = sizeof(*isys_fw_cfg);
359 :
360 1 : return 0;
361 : }
362 :
363 1 : int ipu6_fw_isys_init(struct ipu6_isys *isys, unsigned int num_streams)
364 : {
365 1 : struct device *dev = &isys->adev->auxdev.dev;
366 : int retry = IPU6_ISYS_OPEN_RETRY;
367 1 : struct ipu6_fw_com_cfg fwcom = {
368 : .cell_start = start_sp,
369 : .cell_ready = query_sp,
370 : .buttress_boot_offset = SYSCOM_BUTTRESS_FW_PARAMS_ISYS_OFFSET,
371 : };
372 : int ret;
373 :
374 1 : ipu6_isys_fwcom_cfg_init(isys, &fwcom, num_streams);
375 :
376 2 : isys->fwcom = ipu6_fw_com_prepare(&fwcom, isys->adev,
377 1 : isys->pdata->base);
378 1 : if (!isys->fwcom) {
379 0 : dev_err(dev, "isys fw com prepare failed\n");
380 0 : return -EIO;
381 : }
382 :
383 1 : ret = ipu6_fw_com_open(isys->fwcom);
384 1 : if (ret) {
385 0 : dev_err(dev, "isys fw com open failed %d\n", ret);
386 0 : return ret;
387 : }
388 :
389 : do {
390 : usleep_range(400, 500);
391 1 : if (ipu6_fw_com_ready(isys->fwcom))
392 : break;
393 0 : retry--;
394 0 : } while (retry > 0);
395 :
396 1 : if (!retry) {
397 0 : dev_err(dev, "isys port open ready failed %d\n", ret);
398 0 : ipu6_fw_isys_close(isys);
399 : ret = -EIO;
400 : }
401 :
402 : return ret;
403 : }
404 :
405 : struct ipu6_fw_isys_resp_info_abi *
406 13 : ipu6_fw_isys_get_resp(void *context, unsigned int queue)
407 : {
408 13 : return ipu6_recv_get_token(context, queue);
409 : }
410 :
411 8 : void ipu6_fw_isys_put_resp(void *context, unsigned int queue)
412 : {
413 8 : ipu6_recv_put_token(context, queue);
414 8 : }
415 :
416 1 : void ipu4_fw_isys_dump_stream_cfg(struct device *dev,
417 : struct ipu4_fw_isys_stream_cfg_data_abi *cfg)
418 : {
419 : unsigned int i;
420 :
421 1 : dev_dbg(dev, "---------------------------\n");
422 1 : dev_dbg(dev, "IPU_FW_ISYS_STREAM_CFG_DATA\n");
423 1 : dev_dbg(dev, "---------------------------\n");
424 :
425 1 : dev_dbg(dev, "crop[0] offset: %lx",
426 : (uintptr_t)&cfg->crop[0] - (uintptr_t)cfg);
427 1 : dev_dbg(dev, "input_pins[0] offset: %lx",
428 : (uintptr_t)&cfg->input_pins[0] - (uintptr_t)cfg);
429 1 : dev_dbg(dev, "output_pins[0] offset: %lx",
430 : (uintptr_t)&cfg->output_pins[0] - (uintptr_t)cfg);
431 1 : dev_dbg(dev, "compfmt offset: %lx",
432 : (uintptr_t)&cfg->compfmt - (uintptr_t)cfg);
433 :
434 1 : dev_dbg(dev, "Source %d\n", cfg->src);
435 1 : dev_dbg(dev, "VC %d\n", cfg->vc);
436 1 : dev_dbg(dev, "Nof input pins %d\n", cfg->nof_input_pins);
437 1 : dev_dbg(dev, "Nof output pins %d\n", cfg->nof_output_pins);
438 :
439 2 : for (i = 0; i < cfg->nof_input_pins; i++) {
440 1 : dev_dbg(dev, "Input pin %d\n", i);
441 1 : dev_dbg(dev, "Mipi data type 0x%0x\n",
442 : cfg->input_pins[i].dt);
443 1 : dev_dbg(dev, "Mipi store mode %d\n",
444 : cfg->input_pins[i].mipi_store_mode);
445 1 : dev_dbg(dev, "Bits per pixel %d\n",
446 : cfg->input_pins[i].bits_per_pix);
447 1 : dev_dbg(dev, "Mapped data type 0x%0x\n",
448 : cfg->input_pins[i].mapped_dt);
449 1 : dev_dbg(dev, "Input res width %d\n",
450 : cfg->input_pins[i].input_res.width);
451 1 : dev_dbg(dev, "Input res height %d\n",
452 : cfg->input_pins[i].input_res.height);
453 : }
454 :
455 5 : for (i = 0; i < N_IPU_FW_ISYS_CROPPING_LOCATION; i++) {
456 4 : dev_dbg(dev, "Crop info %d\n", i);
457 4 : dev_dbg(dev, "Crop.top_offset %d\n",
458 : cfg->crop[i].top_offset);
459 4 : dev_dbg(dev, "Crop.left_offset %d\n",
460 : cfg->crop[i].left_offset);
461 4 : dev_dbg(dev, "Crop.bottom_offset %d\n",
462 : cfg->crop[i].bottom_offset);
463 4 : dev_dbg(dev, "Crop.right_offset %d\n",
464 : cfg->crop[i].right_offset);
465 4 : dev_dbg(dev, "----------------\n");
466 : }
467 :
468 2 : for (i = 0; i < cfg->nof_output_pins; i++) {
469 1 : dev_dbg(dev, "Output pin %d\n", i);
470 1 : dev_dbg(dev, "Output input pin id %d\n",
471 : cfg->output_pins[i].input_pin_id);
472 1 : dev_dbg(dev, "Output res width %d\n",
473 : cfg->output_pins[i].output_res.width);
474 1 : dev_dbg(dev, "Output res height %d\n",
475 : cfg->output_pins[i].output_res.height);
476 1 : dev_dbg(dev, "Payload buf size: %d\n",
477 : cfg->output_pins[i].payload_buf_size);
478 1 : dev_dbg(dev, "Stride %d\n", cfg->output_pins[i].stride);
479 1 : dev_dbg(dev, "Pin type %d\n", cfg->output_pins[i].pt);
480 1 : dev_dbg(dev, "Ft %d\n", cfg->output_pins[i].ft);
481 1 : dev_dbg(dev, "Watermar in lines %d\n",
482 : cfg->output_pins[i].watermark_in_lines);
483 1 : dev_dbg(dev, "Send irq %d\n",
484 : cfg->output_pins[i].send_irq);
485 1 : dev_dbg(dev, "Reserve compression %d\n",
486 : cfg->output_pins[i].reserve_compression);
487 1 : dev_dbg(dev, "----------------\n");
488 : }
489 1 : }
490 :
491 : void
492 2 : ipu4_fw_isys_dump_frame_buff_set(struct device *dev,
493 : struct ipu4_fw_isys_frame_buff_set_abi *buf,
494 : unsigned int outputs)
495 : {
496 : unsigned int i;
497 :
498 2 : dev_dbg(dev, "-----------------------------------------------------\n");
499 2 : dev_dbg(dev, "FRAME_BUFF_SET with %d outputs\n", outputs);
500 4 : for (i = 0; i < outputs; i++) {
501 2 : dev_dbg(dev, "output_pin[%d]:\n", i);
502 2 : dev_dbg(dev, "\t.out_buf_id = %llu\n",
503 : buf->output_pins[i].out_buf_id);
504 2 : dev_dbg(dev, "\t.addr = 0x%x\n", buf->output_pins[i].addr);
505 2 : dev_dbg(dev, "\t.compress = %d\n",
506 : buf->output_pins[i].compress);
507 : }
508 :
509 2 : dev_dbg(dev, "send_irq_sof = 0x%x\n", buf->send_irq_sof);
510 2 : dev_dbg(dev, "send_irq_eof = 0x%x\n", buf->send_irq_eof);
511 2 : dev_dbg(dev, "send_resp_sof = 0x%x\n", buf->send_resp_sof);
512 2 : dev_dbg(dev, "send_resp_eof = 0x%x\n", buf->send_resp_eof);
513 2 : dev_dbg(dev, "send_irq_capture_ack = 0x%x\n",
514 : buf->send_irq_capture_ack);
515 2 : dev_dbg(dev, "send_irq_capture_done = 0x%x\n",
516 : buf->send_irq_capture_done);
517 :
518 2 : dev_dbg(dev, "-----------------------------------------------------\n");
519 2 : }
520 :
521 :
522 0 : void ipu6_fw_isys_dump_stream_cfg(struct device *dev,
523 : struct ipu6_fw_isys_stream_cfg_data_abi *cfg)
524 : {
525 : unsigned int i;
526 :
527 0 : dev_dbg(dev, "-----------------------------------------------------\n");
528 0 : dev_dbg(dev, "IPU6_FW_ISYS_STREAM_CFG_DATA\n");
529 :
530 0 : dev_dbg(dev, "compfmt = %d\n", cfg->vc);
531 0 : dev_dbg(dev, "src = %d\n", cfg->src);
532 0 : dev_dbg(dev, "vc = %d\n", cfg->vc);
533 0 : dev_dbg(dev, "isl_use = %d\n", cfg->isl_use);
534 0 : dev_dbg(dev, "sensor_type = %d\n", cfg->sensor_type);
535 :
536 0 : dev_dbg(dev, "send_irq_sof_discarded = %d\n",
537 : cfg->send_irq_sof_discarded);
538 0 : dev_dbg(dev, "send_irq_eof_discarded = %d\n",
539 : cfg->send_irq_eof_discarded);
540 0 : dev_dbg(dev, "send_resp_sof_discarded = %d\n",
541 : cfg->send_resp_sof_discarded);
542 0 : dev_dbg(dev, "send_resp_eof_discarded = %d\n",
543 : cfg->send_resp_eof_discarded);
544 :
545 0 : dev_dbg(dev, "crop:\n");
546 0 : dev_dbg(dev, "\t.left_top = [%d, %d]\n", cfg->crop.left_offset,
547 : cfg->crop.top_offset);
548 0 : dev_dbg(dev, "\t.right_bottom = [%d, %d]\n", cfg->crop.right_offset,
549 : cfg->crop.bottom_offset);
550 :
551 0 : dev_dbg(dev, "nof_input_pins = %d\n", cfg->nof_input_pins);
552 0 : for (i = 0; i < cfg->nof_input_pins; i++) {
553 0 : dev_dbg(dev, "input pin[%d]:\n", i);
554 0 : dev_dbg(dev, "\t.dt = 0x%0x\n", cfg->input_pins[i].dt);
555 0 : dev_dbg(dev, "\t.mipi_store_mode = %d\n",
556 : cfg->input_pins[i].mipi_store_mode);
557 0 : dev_dbg(dev, "\t.bits_per_pix = %d\n",
558 : cfg->input_pins[i].bits_per_pix);
559 0 : dev_dbg(dev, "\t.mapped_dt = 0x%0x\n",
560 : cfg->input_pins[i].mapped_dt);
561 0 : dev_dbg(dev, "\t.input_res = %dx%d\n",
562 : cfg->input_pins[i].input_res.width,
563 : cfg->input_pins[i].input_res.height);
564 0 : dev_dbg(dev, "\t.mipi_decompression = %d\n",
565 : cfg->input_pins[i].mipi_decompression);
566 0 : dev_dbg(dev, "\t.capture_mode = %d\n",
567 : cfg->input_pins[i].capture_mode);
568 : }
569 :
570 0 : dev_dbg(dev, "nof_output_pins = %d\n", cfg->nof_output_pins);
571 0 : for (i = 0; i < cfg->nof_output_pins; i++) {
572 0 : dev_dbg(dev, "output_pin[%d]:\n", i);
573 0 : dev_dbg(dev, "\t.input_pin_id = %d\n",
574 : cfg->output_pins[i].input_pin_id);
575 0 : dev_dbg(dev, "\t.output_res = %dx%d\n",
576 : cfg->output_pins[i].output_res.width,
577 : cfg->output_pins[i].output_res.height);
578 0 : dev_dbg(dev, "\t.stride = %d\n", cfg->output_pins[i].stride);
579 0 : dev_dbg(dev, "\t.pt = %d\n", cfg->output_pins[i].pt);
580 0 : dev_dbg(dev, "\t.payload_buf_size = %d\n",
581 : cfg->output_pins[i].payload_buf_size);
582 0 : dev_dbg(dev, "\t.ft = %d\n", cfg->output_pins[i].ft);
583 0 : dev_dbg(dev, "\t.watermark_in_lines = %d\n",
584 : cfg->output_pins[i].watermark_in_lines);
585 0 : dev_dbg(dev, "\t.send_irq = %d\n",
586 : cfg->output_pins[i].send_irq);
587 0 : dev_dbg(dev, "\t.reserve_compression = %d\n",
588 : cfg->output_pins[i].reserve_compression);
589 0 : dev_dbg(dev, "\t.snoopable = %d\n",
590 : cfg->output_pins[i].snoopable);
591 0 : dev_dbg(dev, "\t.error_handling_enable = %d\n",
592 : cfg->output_pins[i].error_handling_enable);
593 0 : dev_dbg(dev, "\t.sensor_type = %d\n",
594 : cfg->output_pins[i].sensor_type);
595 : }
596 0 : dev_dbg(dev, "-----------------------------------------------------\n");
597 0 : }
598 :
599 : void
600 0 : ipu6_fw_isys_dump_frame_buff_set(struct device *dev,
601 : struct ipu6_fw_isys_frame_buff_set_abi *buf,
602 : unsigned int outputs)
603 : {
604 : unsigned int i;
605 :
606 0 : dev_dbg(dev, "-----------------------------------------------------\n");
607 0 : dev_dbg(dev, "IPU6_FW_ISYS_FRAME_BUFF_SET\n");
608 :
609 0 : for (i = 0; i < outputs; i++) {
610 0 : dev_dbg(dev, "output_pin[%d]:\n", i);
611 0 : dev_dbg(dev, "\t.out_buf_id = %llu\n",
612 : buf->output_pins[i].out_buf_id);
613 0 : dev_dbg(dev, "\t.addr = 0x%x\n", buf->output_pins[i].addr);
614 0 : dev_dbg(dev, "\t.compress = %d\n",
615 : buf->output_pins[i].compress);
616 : }
617 :
618 0 : dev_dbg(dev, "send_irq_sof = 0x%x\n", buf->send_irq_sof);
619 0 : dev_dbg(dev, "send_irq_eof = 0x%x\n", buf->send_irq_eof);
620 0 : dev_dbg(dev, "send_resp_sof = 0x%x\n", buf->send_resp_sof);
621 0 : dev_dbg(dev, "send_resp_eof = 0x%x\n", buf->send_resp_eof);
622 0 : dev_dbg(dev, "send_irq_capture_ack = 0x%x\n",
623 : buf->send_irq_capture_ack);
624 0 : dev_dbg(dev, "send_irq_capture_done = 0x%x\n",
625 : buf->send_irq_capture_done);
626 0 : dev_dbg(dev, "send_resp_capture_ack = 0x%x\n",
627 : buf->send_resp_capture_ack);
628 0 : dev_dbg(dev, "send_resp_capture_done = 0x%x\n",
629 : buf->send_resp_capture_done);
630 :
631 0 : dev_dbg(dev, "-----------------------------------------------------\n");
632 0 : }
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